Associate Professor Masaharu Kobayashi (Institute of Industry Science, Hiramoto-Kobayashi Laboratory) and his colleagues have developed a device that combines an oxide semiconductor IGZO and a resistive non-volatile memory in a three-dimensional stacked array to solve the wiring problem of a two-dimensional array and to enable massively parallel computation, making it possible to physically implement deep learning multilayer neural networks on a single chip. In order to solve the 2-D wiring problem and enable massively parallel computing, the memory array is stacked in 3-D, making it possible to physically implement deep learning multilayer neural networks on a single chip. This makes it possible to implement deep learning not only in the cloud, but also on edge devices. These results were presented at the VLSI Technology Symposium 2020 held from June 14 (Sunday).
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